Sr DFT Engineer
Arrow Electronics

San Jose, California

This job has expired.


Sr DFT Engineer

Job Description:

Experience range : 8+ year
* Scan Implementation for large SoC
* MBIST implementation
* ATPG for different fault model and gate level simulation with and w/o SDF
* Understand DFT architecture and able to solve the issues of DFT
* DFX design front-end checks, Spyglass check, CDC checks
* Timing closure support for DFT Test Mode
* Silicon bring-up support and debugging Silicon failures
Any special or skills related notes:
* Hands on experience with Cadence Scan and ATPG tool - Genus and Modus
* Synopsys SMS tool knowledge for MBIST
* iJTAG and IEEE1500 wrapper understanding.
Education: Bachelor's degree in Engineering

Annual Hiring Range/Hourly Rate:

$108,000.00 - $132,000.00

Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.


US-CA-San Jose, California (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

This job has expired.
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